Test Documentation Hub
Pantheon includes focused GPU diagnostics for compute, memory, interconnect, and AI execution paths. Choose a test for its target subsystem and failure mode.
Core & Compute
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Asynchronously overlaps memory sweeps, FP16 tensor math, FP32 vector math, and SFU work to load multiple GPU pipelines together.
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Uses volatile math to force rapid ALU state switching and expose voltage-rail and VRM stability limits.
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Alternates heavy FMA load and short idle periods to create repeated transient power ramps.
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Saturates FP16 arithmetic with continuous fused multiply-add chains to expose half-precision datapath, power, and thermal issues.
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Uses physical matrix multiply-accumulate instructions to push matrix cores toward sustained thermal and power limits.
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Uses platform-specific matrix instructions to exercise modern transformer-engine and matrix-core execution paths.
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Runs sustained FP64 fused multiply-add work to expose double-precision throughput, clocks, and power behavior.
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Saturates INT32 ALUs with bit operations, rotations, and XOR cascades to isolate integer-specific datapaths.
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Hammers high-latency SIN, COS, EXP, LOG, and reciprocal-square-root operations to exercise special-function units.
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Combines vector ALU work with local-memory bank conflicts for dense thermal and SRAM pressure.
Fixed-Function & Accelerators
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Floods dedicated ray-tracing hardware with non-coherent intersection work and BVH traversal.
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Feeds high-entropy input into the hardware video encoder to exercise fixed-function media logic.
Memory & Cache
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Forces concurrent wide-stride atomic read-modify-write operations to stress L2 arbitration and contention handling.
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Defeats prefetching with dependent pointer-chasing random walks across the memory pool.
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Bypasses cache and heavily unrolls writes with alternating patterns to maximize physical write-path pressure.
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Measures standard sequential VRAM write bandwidth with non-temporal stores and rail-to-rail patterns.
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Uses heavily unrolled volatile pointer accesses to force direct memory fetches without relying on cache reuse.
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Measures standard sequential VRAM read bandwidth using wide, coalesced device reads.
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Strides reads across large page boundaries to drive row-buffer misses in the memory subsystem.
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Forces large numbers of uncoalesced reads to overload memory-controller queues and cache arbitration.
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Writes a known payload, heats the device with compute work, then checks whether memory retention errors occurred.
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Hammers an isolated memory region while drawing compute power to create a severe package thermal gradient.
Interconnect & Architecture
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Saturates peer-to-peer DMA links across NVLink, Infinity Fabric, or PCIe where available.
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Validates a two-GPU sum-and-broadcast collective with direct peer DMA where available and a clearly reported host-staged fallback otherwise.
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Performs pseudo-random jumps across page boundaries to force translation-cache misses and page walks.
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Floods the bus with asynchronous host-to-device and device-to-host DMA transfers.
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Continuously reads a pristine pattern to detect uncorrectable errors and observe active ECC-scrub behavior.
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Alternates high and low data patterns to maximize physical memory-bus toggle rate and TSV or PHY stress.
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Reads from one memory region and writes another to exercise crossbar and pseudo-channel traffic.
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Launches micro-kernels across many streams to pressure dispatcher multiplexing and scheduling behavior.
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Initializes the GPU without compute or memory work so telemetry captures an idle baseline for comparison.
AI & ML
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Lists the inference, training, runtime, RAG, and vision suites, including their commands, telemetry guidance, and diagnostic scope.
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Uses dependent KV-cache gathers and projection-like math to isolate the cache, memory, and compute pressure of autoregressive generation.
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Combines causal context scans and projection-like math to isolate the throughput-oriented pressure of long prompt processing.
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Performs sparse page reads and updates across a synthetic cache to resemble ragged requests and paged KV-cache maintenance.
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Exercises the combined compute and memory-access pattern of causal fused attention, including context-window reuse.
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Applies paired rotary-position-style math to exercise the embedding transform path used by modern transformers.
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Unpacks low-precision values and applies projection-style arithmetic to expose quantization and dequantization overhead.
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Creates mixed execution pressure representative of requests with different prompt and generation demands, without claiming queue-level serving metrics.
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Exercises the alternating draft and verification style of speculative decoding to reveal its compute and cache interaction.
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Uses sparse Top-K-style routing and gated accumulation to exercise the local compute path behind mixture-of-experts inference.
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Applies forward, backward, gradient, and optimizer-style arithmetic to create a controlled training-step pressure profile.
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Repeatedly drives a working-set allocation pattern to help expose allocator pressure and memory-management instability.
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Repeats a compact launch sequence to stress graph-capture and replay-adjacent runtime behavior without requiring a model framework.
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Applies embedding-vector projection work to stress the dense math and memory behavior relevant to retrieval and RAG pipelines.
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Applies image-tile projection work to stress the dense compute and memory behavior common in vision encoder front ends.